philips semiconductors product specification n-channel logic level trenchmos ? transistor PSMN004-55W features symbol quick reference data ? 'trench' technology v dss = 55 v ? very low on-state resistance ? fast switching i d = 100 a ? low thermal resistance ? logic level compatible r ds(on) 4.2 m w (v gs = 10 v) r ds(on) 4.5 m w (v gs = 5 v) r ds(on) 5 m w (v gs = 4.5 v) general description pinning sot429 (to247) siliconmax products use the latest pin description philips trench technology to achieve the lowest possible 1 gate on-state resistance in each package at each voltage rating. 2 drain applications:- 3 source ? d.c. to d.c. converters ? switched mode power supplies tab drain the PSMN004-55W is supplied in the sot429 (to247) conventional leaded package. limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit v dss drain-source voltage t j = 25 ?c to 175?c - 55 v v dgr drain-gate voltage t j = 25 ?c to 175?c; r gs = 20 k w -55v v gs continuous gate-source - 15 v voltage v gsm peak pulsed gate-source t j 150 ?c - 20 v voltage i d continuous drain current t mb = 25 ?c; v gs = 5 v - 100 1 a t mb = 100 ?c; v gs = 5 v - 100 1 a i dm pulsed drain current t mb = 25 ?c - 300 a p d total power dissipation t mb = 25 ?c - 300 w t j , t stg operating junction and - 55 175 ?c storage temperature d g s 2 3 1 1 maximum continuous current limited by package. october 1999 1 rev 1.100
philips semiconductors product specification n-channel logic level trenchmos ? transistor PSMN004-55W avalanche energy limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit e as non-repetitive avalanche unclamped inductive load, i as = 100 a; - 357 mj energy t p = 100 m s; t j prior to avalanche = 25?c; v dd 25 v; r gs = 50 w ; v gs = 5 v; refer to fig:15 i as non-repetitive avalanche - 100 a current thermal resistances symbol parameter conditions min. typ. max. unit r th j-mb thermal resistance junction - - 0.5 k/w to mounting base r th j-a thermal resistance junction in free air - 45 - k/w to ambient electrical characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit v (br)dss drain-source breakdown v gs = 0 v; i d = 0.25 ma; 55 - - v voltage t j = -55?c 42 - - v v gs(to) gate threshold voltage v ds = v gs ; i d = 1 ma 1 1.5 2 v t j = 175?c 0.5 - - v t j = -55?c - - 2.3 v r ds(on) drain-source on-state v gs = 10 v; i d = 25 a - 3.2 4.2 m w resistance v gs = 5 v; i d = 25 a - 3.6 4.5 m w v gs = 4.5 v; i d = 25 a - 3.8 5 m w v gs = 5 v; i d = 25 a; t j = 175?c - 6.2 9.5 m w i gss gate-source leakage current v gs = 10 v; v ds = 0 v; - 0.02 100 na i dss zero gate voltage drain v ds = 55 v; v gs = 0 v; - 0.05 10 m a current t j = 175?c - - 500 m a q g(tot) total gate charge i d = 100 a; v dd = 44 v; v gs = 5 v - 226 - nc q gs gate-source charge - 36 - nc q gd gate-drain (miller) charge - 106 - nc t d on turn-on delay time v dd = 30 v; r d = 1.2 w ; - 26 - ns t r turn-on rise time v gs = 10 v; r g = 5.6 w - 118 - ns t d off turn-off delay time resistive load - 848 - ns t f turn-off fall time - 336 - ns l d internal drain inductance measured tab to centre of die - 3.5 - nh l d internal drain inductance measured from drain lead to centre of die - 4.5 - nh l s internal source inductance measured from source lead to source - 7.5 - nh bond pad c iss input capacitance v gs = 0 v; v ds = 25 v; f = 1 mhz - 13 - nf c oss output capacitance - 1900 - pf c rss feedback capacitance - 1250 - pf october 1999 2 rev 1.100
philips semiconductors product specification n-channel logic level trenchmos ? transistor PSMN004-55W reverse diode limiting values and characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit i s continuous source current - - 100 a (body diode) i sm pulsed source current (body - - 300 a diode) v sd diode forward voltage i f = 25 a; v gs = 0 v - 0.78 1.2 v i f = 75 a; v gs = 0 v - 0.92 - t rr reverse recovery time i f = 20 a; -di f /dt = 100 a/ m s; - 150 - ns q rr reverse recovery charge v gs = -10 v; v r = 20 v - 0.7 - m c october 1999 3 rev 1.100
philips semiconductors product specification n-channel logic level trenchmos ? transistor PSMN004-55W fig.1. normalised power dissipation. pd% = 100 p d /p d 25 ?c = f(t mb ) fig.2. normalised continuous drain current. id% = 100 i d /i d 25 ?c = f(t mb ); conditions: v gs 3 5 v fig.3. safe operating area. t mb = 25 ?c i d & i dm = f(v ds ); i dm single pulse; parameter t p fig.4. transient thermal impedance. z th j-mb = f(t); parameter d = t p /t fig.5. typical output characteristics, t j = 25 ?c . i d = f(v ds ) fig.6. typical on-state resistance, t j = 25 ?c . r ds(on) = f(i d ) normalised power derating, pd (%) 0 10 20 30 40 50 60 70 80 90 100 0 25 50 75 100 125 150 175 mounting base temperature, tmb (c) 0.001 0.01 0.1 1 1e-06 1e-05 1e-04 1e-03 1e-02 1e-01 1e+00 pulse width, tp (s) transient thermal impedance, zth j-mb (k/w) single pulse d = 0.5 0.2 0.1 0.05 0.02 tp d = tp/t d p t normalised current derating, id (%) 0 10 20 30 40 50 60 70 80 90 100 0 25 50 75 100 125 150 175 mounting base temperature, tmb (c) 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 drain-source voltage, vds (v) drain current, id (a) 2.2 v tj = 25 c vgs = 10v 2.3 v 2.4 v 2.5 v 2 v 10 v 2.1 v 1 10 100 1000 1 10 100 drain-source voltage, vds (v) peak pulsed drain current, idm (a) d.c. 100 ms 10 ms rds(on) = vds/ id 1 ms tp = 10 us 100 us 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 102030405060708090100 drain current, id (a) drain-source on resistance, rds(on) (ohms) vgs = 10v tj = 25 c 2.4 v 5 v 2.5 v 2.2 v 2.3 v 2 v 2.1 v october 1999 4 rev 1.100
philips semiconductors product specification n-channel logic level trenchmos ? transistor PSMN004-55W fig.7. typical transfer characteristics. i d = f(v gs ) fig.8. typical transconductance, t j = 25 ?c . g fs = f(i d ) fig.9. normalised drain-source on-state resistance. r ds(on) /r ds(on)25 ?c = f(t j ) fig.10. gate threshold voltage. v gs(to) = f(t j ); conditions: i d = 1 ma; v ds = v gs fig.11. sub-threshold drain current. i d = f(v gs) ; conditions: t j = 25 ?c; v ds = v gs fig.12. typical capacitances, c iss , c oss , c rss . c = f(v ds ); conditions: v gs = 0 v; f = 1 mhz 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 gate-source voltage, vgs (v) drain current, id (a) vds > id x rds(on) tj = 25 c 175 c threshold voltage, vgs(to) (v) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 junction temperature, tj (c) typical maximum minimum 0 20 40 60 80 100 120 140 160 180 200 220 0 102030405060708090100 drain current, id (a) transconductance, gfs (s) tj = 25 c 175 c vds > id x rds(on) drain current, id (a) 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 0 0.5 1 1.5 2 2.5 3 gate-source voltage, vgs (v) minimum typical maximum normalised on-state resistance 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 junction temperature, tj (c) 100 1000 10000 100000 0.1 1 10 100 drain-source voltage, vds (v) capacitances, ciss, coss, crss (pf) ciss coss crss october 1999 5 rev 1.100
philips semiconductors product specification n-channel logic level trenchmos ? transistor PSMN004-55W fig.13. typical turn-on gate-charge characteristics. v gs = f(q g ) fig.14. typical reverse diode current. i f = f(v sds ); conditions: v gs = 0 v; parameter t j fig.15. maximum permissible non-repetitive avalanche current (i as ) versus avalanche time (t av ); unclamped inductive load 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 40 80 120 160 200 240 280 320 360 400 440 gate charge, qg (nc) gate-source voltage, vgs (v) id = 100 a tj = 25 c vdd = 11 v vdd = 44 v 1 10 100 1000 0.001 0.01 0.1 1 10 avalanche time, t av (ms) maximum avalanche current, i as (a) tj prior to avalanche = 150 c 25 c 0 10 20 30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 source-drain voltage, vsds (v) source-drain diode current, if (a) tj = 25 c 175 c vgs = 0 v october 1999 6 rev 1.100
philips semiconductors product specification n-channel logic level trenchmos ? transistor PSMN004-55W mechanical data fig.16. sot429; pin 2 connected to mounting base notes 1. observe the general handling precautions for electrostatic-discharge sensitive devices (esds) to prevent damage to mos gate oxide. 2. refer to mounting instructions for sot429 envelope. 3. epoxy meets ul94 v0 at 1/8". references outline version european projection issue date iec jedec eiaj sot429 to-247 98-04-07 99-08-04 0 10 20 mm scale plastic single-ended through-hole package; heatsink mounted; 1 mounting hole; 3-lead to-247 sot429 e p a a 1 b w m b 12 3 e e b 1 b 2 c q q l y r d s l 1 (1) a unit a 1 d b e e w s r q q p ly b 2 b 1 c l 1 (1) dimensions (mm are the original dimensions) a b a mm 17 13 6 4 5.3 4.7 1.9 1.7 2.2 1.8 1.2 0.9 3.2 2.8 0.9 0.6 21 20 16 15 5.45 3.7 3.3 2.6 2.4 5.3 7.5 7.1 0.4 15.7 15.3 16 15 4.0 3.6 3.5 3.3 note 1. tinning of terminals are uncontrolled within zone l 1 . october 1999 7 rev 1.100
philips semiconductors product specification n-channel logic level trenchmos ? transistor PSMN004-55W definitions data sheet status objective specification this data sheet contains target or goal specifications for product development. preliminary specification this data sheet contains preliminary data; supplementary data may be published later. product specification this data sheet contains final product specifications. limiting values limiting values are given in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of this specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. philips electronics n.v. 1999 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. october 1999 8 rev 1.100
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